Synopsys Taiwan Co., Ltd._台灣新思科技股份有限公司
English Required
IC設計類:DDR IP Design Verification Engineer (熟悉UVM/SystemVerilog)
10/15 Updated
Full-time
Manager/Director
English RequiredSalary & Location
Salary negotiable
(Regular monthly salary of NT$40,000 or above)
新竹縣竹北市
Required
Language Requirements
English
聽/中等、說/中等、讀/中等、寫/中等
Work Experience
5年以上
Job Description
請務必上官網投遞履歷:hhttps://careers.synopsys.com/job/hsinchu/ddr-design-verification-engineer/44408/70025496208
Digital IP Verification, Staff Engineer
Our group is working is working on cutting edge DDR controller design and verification targeting the current and next generation DDR technology, such as DDR5, LPDDR6.
The position offers an excellent opportunity for a highly experienced verification engineer to work with a professional team of digital engineers responsible for delivering high-end designs from specification development to performing functional verification, performance analysis down to successful IP releases.
The controller IP development is very dynamic and provides an endless list of challenges. This work is very challenging, not only given the constant technological changes but also given the ownership and the need to charter unknown waters.
Does this sound like a good role for you?
Responsibility and Key Qualification
• This position is for leading edge IP verification.
• Study standard specifications published by JEDEC.
• Work on UVM methodology-based verification platform.
• Study design micro architecture, implement high quality verification from defining verification spec, planning and implement infrastructure, down to analyze and debug regression failures, and reach full function coverage.
• Work with design team to debug and fix RTL issues.
• Work with VIP teams for VIP issues
• Must be self-motivated, proactive, and able to achieve good quality while meeting tight deadlines.
• Mentor junior engineers and work with multiple team members.
• Good communication skills for interacting between different design groups and customer support teams are required.
Preferred Experience
• MSEE plus with a minimum of 5 years of experience in UVM-based verification methodology. And demonstrates good analysis and problem-solving skills.
• Knowledgeable and experienced in UVM, assertions. Skills in Formal verification is a plus.
• Knowledgeable in DDR is a plus.
• Solid theoretical and practical background in AXI, CHI, CRYPTO and RAS is a solid plus.
• Scripting experience in Shell, Perl, Python and TCL is a plus.
• Be fluent in English, both speaking and writing.
• Demonstrates good attitude in teamwork.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Educational Requirements
碩士以上
Field of Study Requirements
資訊工程相關、電機電子工程相關
Work Schedule
日班
Leave Policy
依公司規定
Job Category
Digital IC Design Engineer
新竹市
電腦軟體服務業
▎關於Synopsys
新思科技名列美國標普500指數成分股，長期以來是全球排名第一的IC電子設計自動化（EDA）創新公司，也是排名第一的IC介面IP供應廠商，專門提供「矽晶到軟體（Silicon to Software™）」最佳的解決方案。不論是針對開發先進半導體系統單晶片（SoC）的設計工程師，或正在撰寫應用程式且要求高品質及安全性的軟體開發工程師，新思科技都能提供所需的解決方案，以協助工程師完成創新、高品質並兼具安全性的產品。更多詳情請造訪： http://www.synopsys.com。
新思科技1991年在台灣成立分公司，並於2012年底合併思源科技，目前員工總人數已達1300位，其中有超過500位的研發人才，是在台灣的跨國軟體企業中，擁有最大規模研發團隊的公司之一。新思科技持續為台灣培養半導體設計軟體人才，加速國內廠商產品開發與問市的時程，強化台灣在半導體國際市場的競爭力。
Synopsys注重包容性和多樣性，我們歡迎並考慮所有不同種族、膚色、宗教、國籍、性別、性取向、性別認同、年齡、退伍軍人或身心障礙的應徵者。
Synopsys 國內外獎項:
★2024 Great Place to Work 卓越職場認證
★2024 Most loved place
★ 2023美國 Comparably Best Place To Work Awards 4大獎項: Diversity, Women, Culture, CEO
★2023 CandE award winner in APAC
★2023天下人才永續獎 外商組 第三名
★2023育部體育署 運動企業認證
★2023台北市職場性平認證 金質獎
★2023人力銀行幸福企業科技研發業 金獎
★2023新竹科學園區 友善職場工作平權 特優獎
新思台灣持續響應「2024 TALENT, in Taiwan，台灣人才永續行動聯盟」倡議與400+聯盟夥伴共同推動人才培育的希望工程，以實際行動強化人才競爭力。
2024年，我們秉持多元與共融理念，持續深耕在地並致力於人才培育，與台灣半導體產業共同成長茁壯，以提升台灣人才在半導體國際市場的競爭力，並期盼人人都能發揮潛能與優勢，為企業卓越與個人職場，寫下亮麗的篇章。
▎關於我們 - Synopsys TAIWAN official website
https://www.synopsys.com/zh-tw/taiwan/about-us.html
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