【本職缺優先審核至高通官網投遞人選】 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 Apply here: https://careers.qualcomm.com/careers/job/446715508111 【Job Overview】 The Qualcomm Memory System/Technology Team in Process & Package Solutions Group has an opening in the areas of custom DRAM design and architecture for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will design circuits for the custom DRAM to improve system KPIs such as bandwidth, latency, power, thermal, and area efficiency. The candidate will work on solutions addressing manufacturability and repairability of the circuits. The candidate is expected to know the DRAM circuit design in the domains of DRAM bank circuits such as decoder, sense amplifier, datapath, and voltage generation circuits. The candidate should have familiarity with the bus and compute fabrics as well as advanced packaging and 3D integration. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential. 【Responsibilities】 • Architect, design, and implement high-speed PHY circuits • Create layouts that optimize circuit placement, signal routing, and power delivery • Develop robust power delivery to the PHY design • Simulate signal integrity and SNR performance together with the package and board s-parameter model • Simulate pre-layout and post-layout mixed-mode circuits under PVT corners • Incorporate power management features to reduce energy consumption • Use state-of-the-art design and simulation tools to simulate the circuit behavior and manufacturability readiness • Develop behavioral, timing, and power models of the circuits to guide the architecture choices across AI, compute, and mobile workloads • Floorplan PHY circuits under manufacturing constraints, testability, repairability, and high performance

【本職缺優先審核至高通官網投遞人選】 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 Apply here: https://careers.qualcomm.com/careers/job/446715508019 【Job Overview】 The Qualcomm Memory System/Technology Team in Process & Package Solutions Group has an opening in the areas of custom DRAM design and architecture for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will design circuits for the custom DRAM to improve system KPIs such as bandwidth, latency, power, thermal, and area efficiency. The candidate will work on solutions addressing manufacturability and repairability of the circuits. The candidate is expected to know the DRAM circuit design in the domains of DRAM bank circuits such as decoder, sense amplifier, datapath, and voltage generation circuits. The candidate should have familiarity with the bus and compute fabrics as well as advanced packaging and 3D integration. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential. 【Responsibilities】 • Develop and optimize 3D DRAM bank organization and near-memory computing architectures to achieve high density, high TOPS/mm2, and high TOPS/W •Develop and validate models for 3D DRAM performance, power, and yield as function of bank, TSV, and power distribution choices •Develop novel fabrics for best/robust distribution of high-bandwidth data from 3D DRAM memory arrays to the near-memory computing units across various workloads for mobile, compute, and XR applications •Develop power distribution topology that enable robust DRAM operation in the 3D stack •Simulate and emulate system performance of 3D DRAM architecture choices across AI, compute, and mobile workloads •Floorplan 3D DRAM chips and design memory array control structures under 3D integration manufacturing constraints, testability, repairability, and high performance

【本職缺優先審核至高通官網投遞人選】 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 Apply here: https://careers.qualcomm.com/careers/job/446715508109 【Job Overview】 The Qualcomm Memory System/Technology Team in Process & Package Solutions Group has an opening in the areas of custom DRAM design and architecture for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will design circuits for the custom DRAM to improve system KPIs such as bandwidth, latency, power, thermal, and area efficiency. The candidate will work on solutions addressing manufacturability and repairability of the circuits. The candidate is expected to know the DRAM circuit design in the domains of DRAM bank circuits such as decoder, sense amplifier, datapath, and voltage generation circuits. The candidate should have familiarity with the bus and compute fabrics as well as advanced packaging and 3D integration. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential. 【Responsibilities】 • Design and optimize memory core circuits for higher sense margin, improved array timing, area • Develop and optimize DRAM circuits and timing control for performant, area, and energy efficient cell array • Develop bank array placement strategies across various bank array, TSV, and power distribution choices • Develop novel fabrics for best/robust distribution of high-bandwidth busses across the DRAM array, compute, and IO • Create layouts that optimize circuit placement, signal routing, and power delivery • Develop robust power delivery to the array design • Use state-of-the-art design and simulation tools to simulate the circuit behavior and manufacturability readiness • Develop behavioral, timing, and power models of the circuits to guide the architecture choices across AI, compute, and mobile workloads • Floorplan DRAM circuits under manufacturing constraints, testability, repairability, and high performance

【本職缺優先審核至高通官網投遞人選】 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 Apply here: https://careers.qualcomm.com/careers/job/446715508110 【Job Overview】 The Qualcomm Memory System/Technology Team in Process & Package Solutions Group has an opening in the areas of custom DRAM design and architecture for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will design bus circuits and power distribution network for the custom DRAM to improve system KPIs such as bandwidth, latency, power, and thermal. The candidate will work on solutions of high-speed and high-bandwidth bus design for advanced memory. The candidate should have familiarity with the bus and compute fabrics as well as advanced packaging and 3D integration. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential. 【Responsibilities】 -Develop and optimize circuits for high-bandwidth memory bus and PDN control, timing, and control -Analyze and ensure the integrity of signals on the bus and PDN across PVT corners -Develop and validate the bus behavior for various access protocols to meet throughput, latency, and energy specifications -Develop novel fabrics for best/robust distribution of high-bandwidth busses and PDN across the DRAM array, compute, and IO -Create layouts that optimize the bus and PDN placement for routability across the whole chip -Use state-of-the-art design and simulation tools to simulate the bus behavior and manufacture readiness -Develop behavioral, timing, and power models of the bus to guide the architecture choices across AI, compute, and mobile workloads -Develop power modeling framework to build state-dependent power and determine PMIC requirements -Floorplan 3D DRAM chips under 3D integration manufacturing constraints, testability, repairability, and high performance

1. Computer troubleshooting and repair. 2. Information system management and maintenance. 3. Procurement, acceptance, and closure of computer-related equipment. 4. IT server room management and maintenance. 5. Information system project requirement analysis, planning, implementation, deployment, management, and maintenance. 6. Handling tasks assigned by supervisors.

Job Title: NPU Modeling Engineer Job Description: Overview: We are seeking an experienced NPU Architect to join our team. As an NPU Architect, you will play a crucial role in designing and implementing the hardware model for our Neural Processing Unit. Your expertise will be instrumental in ensuring efficient and accurate execution of neural network workloads on our NPU. Responsibilities: 1. NPU Architecture Design: • Collaborate with cross-functional teams to define the architecture and specifications for the NPU. • Design the NPU's core components, including the PE array, memory hierarchy, and control logic. • Optimize for performance, power efficiency, and scalability. 2. Bit-True Hardware Model Implementation: • Develop a bit-true hardware model of the NPU in C language. • Ensure that the model accurately represents the NPU's behavior, including arithmetic operations, memory access, and control flow. • Validate the model against reference neural network workloads. 3. Cycle-Accurate Modeling: • Create a cycle-accurate model of the NPU to simulate its behavior at the clock cycle level. • Account for pipeline stages, data dependencies, and timing constraints. • Use tools like Verilog, system-Verilog, or specialized simulation environments to achieve cycle-accurate modeling. 4. Performance Analysis and Optimization: • Profile the NPU model to identify bottlenecks and areas for improvement. • Propose and implement optimizations to enhance performance and reduce latency. • Collaborate with software teams to fine-tune the NPU's behavior. 5. Verification and Validation: • Create testbenches and test vectors to validate both the bit-true and cycle-accurate models. • Conduct functional and performance testing to ensure correctness and compliance with specifications. • Debug and resolve any discrepancies between the models and the actual NPU. 6. Documentation and Communication: • Document the NPU architecture, design decisions, and implementation details. • Present findings, progress, and challenges to stakeholders and management. • Collaborate with software engineers, firmware developers, and system architects. Qualifications: • Master's or Ph.D. degree in Electrical Engineering, Computer Science, or a related field. • Minimum of 3 years of experience in NPU architecture design and implementation. • Proficiency in C/C++/Verilog/System-Verilog programming for hardware modeling. • Familiarity with systolic arrays, matrix multiplication, and neural network accelerators. • Knowledge of bit-true modeling, fixed-point arithmetic, and floating-point arithmetic. • Experience with verification tools and simulation environments. • Strong analytical and problem-solving skills. • Excellent communication and teamwork abilities. • Attention to detail and commitment to quality. If you are passionate about NPU architecture, hardware modeling, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI!

Job Title: AI Compiler Engineer Job Description: Overview: We are seeking a skilled and motivated AI Compiler Engineer to lead the development of our AI compiler for the Neural Processing Unit (NPU). As part of our team, you will play a critical role in transforming high-level neural network workloads (such as CNNs and transformer models) into efficient machine code that maximizes inference performance, minimizes power consumption, and optimizes memory usage. Responsibilities: 1. Compiler Development: • Design and develop an AI compiler that translates high-level neural network descriptions (in frameworks like TensorFlow, PyTorch, or ONNX) into optimized machine code for the NPU. • Implement parsing algorithms to analyze neural network graphs and extract relevant information for compilation. 2. Optimization Strategies: • Optimize the computational graph by applying techniques such as operator fusion, kernel selection, and memory layout transformations. • Minimize inference time, reduce power consumption, and optimize memory footprint through intelligent code generation. 3. Performance Profiling and Analysis: • Profile compiled code to identify bottlenecks and areas for improvement. • Collaborate with hardware architects to understand NPU microarchitecture and tailor optimizations accordingly. 4. Code Generation and Lowering: • Generate efficient machine code from the intermediate representation of neural network operations. • Ensure compatibility with the NPU's instruction set architecture. 5. Integration and Testing: • Integrate the AI compiler into the overall software stack, including runtime libraries and drivers. • Develop test suites to validate correctness, performance, and compatibility across various neural network models. 6. Documentation and Communication: • Document design decisions, algorithms, and implementation details. • Collaborate with cross-functional teams, including hardware engineers, software developers, and researchers. Qualifications: • Master's or Ph.D. in Computer Science, Electrical Engineering, or a related field. • Minimum of 3 years of experience in compiler development, preferably with exposure to AI or machine learning. • Proficiency in C/C++/Python programming and familiarity with compiler construction. • Knowledge of neural network frameworks (TensorFlow, PyTorch, etc.) and their intermediate representations. • Experience with performance profiling tools and optimization techniques. • Understanding of machine learning concepts and hardware architectures. • Familiarity with data structures, optimization algorithms, and DevOps tools (such as Git, CI/CD pipelines). • Strong problem-solving abilities and attention to detail. • Excellent communication skills for collaborating with cross-functional teams. Preferred Skills: • Familiarity with deep learning frameworks and libraries. • Knowledge of hardware acceleration technologies and frameworks. • Experience of tensor computation and optimization. • Previous work in compiler for CPU, GPU, DSP, NPU is a plus. If you are passionate about compiler engineering, AI optimization, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI acceleration.

讓我們跨越國界，千里來相逢，用AI展翅翱翔，來尋找千載難逢的機會 (Tranxform.com 千逢科技) Hardware design verification : • Develop verification environment. • Co-work with hardware designers to verify designs with system verilog and system verilog assertion. • Building, maintaining testbenches and their components using UVM-based methods. • Functional coverage and code coverage. • Generating the random testcases for NPU design,and providing debug reports. • Develop the auto-verifying environment using scripting languages like Perl and Python. Programming Languages: Strong programming skills in languages like System Verilog, Verilog and possibly high-level languages like C/C++. Experience in AI/ML: In-depth knowledge of artificial intelligence and machine learning algorithms. NPU Architecture: Proficiency in designing Neural Processing Unit architectures. Parallel Processing: Understanding of parallel processing and optimization techniques for neural networks. Team Collaboration: Effective communication and collaboration skills within a multidisciplinary team. Problem-solving: Strong analytical and problem-solving skills to address complex design challenges. Knowledge of Industry Trends: Awareness of the latest trends and advancements in NPU technology and AI hardware. Results-Driven: A proactive and results-driven mindset, aiming for high-quality outcomes. Ownership Mentality: Willingness to take ownership and responsibility for the design process. Adaptability: Ability to adapt to evolving technologies and project requirements. Advanced Degree: Typically, a relevant advanced degree (Master's or Ph.D.) in Electrical Engineering, Computer Science, or a related field.

We are seeking a detail-oriented and proactive Sales and Operations Management partner with expertise in operations processes and customer demand management. This role will be responsible for managing overseas business operations and ensuring customer satisfaction through effective coordination and strategic planning. Products: Industrial AI Camera moduels, systems , platforms. Responsibilities: *Sales Coordination – Collaborate closely with the ODM/OEM/JDM Business Development and Account Sales teams to maintain seamless communication and coordination with Engineering, Procurement, and Factory teams. Ensure that projects stay on schedule for ramp-up and mass production phases. Assist in achieving overall sales targets and enhancing operational efficiency, contributing to the success of both short-term and long-term business goals. * Forecast, Order and Sales Forecast Management – Oversee forecast and order processing and provide accurate sales forecasts to support business planning. This includes preparing for long lead-time parts, arranging production line schedules, and managing production capacity to ensure timely order fulfillment. *Material Preparation and Management – Work with customers to review and prepare for long lead-time parts, minimum order quantities (MOQs), and lead times. Optimize material management to prevent shortages and negotiate solutions for excess inventory, ensuring that material requirements align with business needs. *Accounts Receivable Management – Ensure timely collection of payments and manage accounts receivables to maintain a healthy cash flow.

Job Title: Generative AI Models Optimization Engineer - NPU Hardware Job Description: Overview: We are seeking a skilled and innovative Generative AI Models Optimization Engineer to join our dynamic team. In this role, you will be responsible for developing and optimizing generative AI models specifically tailored for Neural Processing Unit (NPU) hardware. As a key member of our AI research and development team, you will play a crucial role in advancing the efficiency and performance of our cutting-edge AI applications. Responsibilities: Generative AI Model Development: Design, implement, and optimize generative AI models for deployment on NPU hardware. Collaborate with cross-functional teams to understand application requirements and tailor models for specific use cases. NPU Hardware Optimization: Analyze and profile NPU hardware architecture to identify optimization opportunities. Implement and fine-tune algorithms to maximize performance and minimize resource utilization on NPUs. Performance Evaluation: Conduct rigorous testing and performance evaluations to ensure generative AI models meet quality standards and deliver optimal results on NPU hardware. Collaborate with QA teams to establish benchmarking criteria and validate model performance across various scenarios. Algorithmic Efficiency: Work on enhancing algorithmic efficiency to ensure that generative AI models are capable of real-time generation while maintaining high-quality outputs. Implement and experiment with state-of-the-art techniques for model compression and quantization. Collaboration: Collaborate with hardware engineers, software developers, and researchers to integrate optimized models into end-to-end AI systems. Provide technical expertise and guidance to cross-functional teams. Documentation: Document optimization methodologies, best practices, and performance results. Create clear and comprehensive documentation for both technical and non-technical stakeholders. Qualifications: Master's or Ph.D. in Computer Science, Electrical Engineering, or a related field. Proven experience in developing and optimizing generative AI models. Solid understanding of Neural Processing Unit (NPU) architecture and hardware constraints. Proficiency in programming languages such as Python, TensorFlow, PyTorch, or C++. Experience with model compression, quantization, and other optimization techniques. Strong problem-solving skills and the ability to work in a collaborative team environment. Preferred Skills: Familiarity with deep learning frameworks and libraries. Knowledge of hardware acceleration technologies and frameworks. Experience with parallel computing and distributed systems. Previous work on AI applications in computer vision, natural language processing, or speech recognition is a plus. If you are passionate about pushing the boundaries of AI optimization on NPU hardware and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of generative AI applications.

讓我們跨越國界，千里來相逢，用AI展翅翱翔，來尋找千載難逢的機會 (Tranxform.com 千逢科技) Hardware Design • Generative AI NPU design and hardware architecture • Memory system design (cache controller, DRAM controller) • Interconnect/Fabric design • Low power technology expertise • High-speed interface design (HW/SW collaboration) • High-performance virtualization designs Programming Languages: Strong programming skills in languages like Verilog and possibly high-level languages like C/C++. Experience in AI/ML: In-depth knowledge of artificial intelligence and machine learning algorithms. NPU Architecture: Proficiency in designing Neural Processing Unit architectures. Parallel Processing: Understanding of parallel processing and optimization techniques for neural networks. Team Collaboration: Effective communication and collaboration skills within a multidisciplinary team. Problem-solving: Strong analytical and problem-solving skills to address complex design challenges. Knowledge of Industry Trends: Awareness of the latest trends and advancements in NPU technology and AI hardware. Results-Driven: A proactive and results-driven mindset, aiming for high-quality outcomes. Ownership Mentality: Willingness to take ownership and responsibility for the design process. Adaptability: Ability to adapt to evolving technologies and project requirements. Advanced Degree: Typically, a relevant advanced degree (Master's or Ph.D.) in Electrical Engineering, Computer Science, or a related field.

1.開發東南亞地區潛在ASIC客戶 2.建立當地長期客戶關係，定期拜訪與維護既有客戶 3.蒐集市場趨勢、競爭者資訊、客戶技術需求，評估 ASIC 商機 4.與客戶進行合約條款協商，協同法務完成簽約流程 5.與內部研發團隊協調合作，追蹤案件進度，以順利完成交付

1. 收集及建立勞工安全衛生作業計畫。 2. 執行公司內、外部安全衛生業務。 3. 處理突發之勞工安全衛生事宜。 4. 執行安全衛生教育訓練。 5. 配合總公司執行ISO45001 系統建置 6. 主管交辦事項

1. 負責海外地區消費性IC產品業務拓展。 2. 代理商關係維護管理及市場開發。 3. 蒐集市場情報，並擬定及分析行銷策略和價格策略。

1. 問題分析(異常,處理) 2. 客戶服務(了解客戶問題,提共解決方案,客戶溝通) 3. 必要時到客戶端(國內) 4. 內部溝通

1.確認影像品質相關需求與規格 2.影像品質調試與問題分析解決 3.協力廠商的影像品質驗收確認

1.網站的維護與內容、功能更新 2.後端網頁系統開發、資料庫程式開發 3.網站系統架構規劃及設計 4.具備基本前端架構及模組分析設計的能力 5.熟悉HTML5/CSS3/Javascript /jQuery，RWD與UI/UX觀念

1. 具自動化視覺檢測設備開發經驗 2. 基本光學(相機、鏡頭、光源、模組)設計與規劃 3. 具Halcon 程式設計能力 4. 熟C#物件化程式架構 5. 二年以上工作經驗

1.機台設備交機(國內外) 2.配合公司派遣 3.協助客戶技術問題排除(線上or現場) 4.配合公司各項支援 5.能與客戶保持良好互動

1.自動化設備流程規劃設計與設備電控成本估價 2.電氣控制回路圖設計﹑繪製(AUTOCAD)及BOM表製作 3.伺服馬達﹑步進馬達﹑線性馬達控制與調校 4.工業配電 5.機械手臂程式與控制