Salary & Location
Salary negotiable
(Regular monthly salary of NT$40,000 or above)
新竹市
Required
Work Experience
不拘
Job Description
1. Design verification with SystemVerilog/UVM, C/C++
2. Integration test environment with VIP
3. Develop checker and scoreboard.
4. Verify design with SystemVerilog assertion.
5. Test plan for a verification task.
[Requirement]
1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming.
2. Better to have SoC design and bus concept.
Number of Openings
2~3人
Educational Requirements
大學(學院)以上
Field of Study Requirements
電機電子工程相關、其他工程相關
Work Schedule
日班
Leave Policy
週休二日
Job Skills
Hardware Language Programming
Digital Chip Product Development
Digital Circuit Analysis & Design
Digital Circuit Verification
撰寫硬體語言程式 數位晶片產品開發 數位電路分析設計 數位電路驗證
Job Category
Electronics Engineers
Digital IC Design Engineer
