Qualcomm Semiconductor Corporation_高通半導體有限公司
IO Characterization and Modeling Engineer (Hsinchu)(3065676)
2/11 更新
全職
初階
英文 條件要求
11 ~ 30 應徵者

職務概況

待遇面議
(經常性薪資達 4 萬元或以上)
新竹市

條件要求

語文條件
英文
聽/精通、說/精通、讀/精通、寫/精通
工作經歷
不拘

職務描述

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表:https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/IO-Characterization-and-Modeling-Engineer_3065676
【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】
https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/IO-Characterization-and-Modeling-Engineer_3065676
【Job Overview】
This is a Verilog modeling and characterization engineer position in Methodology, Flow and Design Kit team involved in defining methodologies, flows and in delivering design kit including behavioral models and timing models for I/Os, memories and standard cell libraries in state of art CMOS/FinFET technology nodes for Qualcomm's advanced mobile baseband, Auto, IOE/IOT & consumer products.
【Job Responsibilities】
.Write RTL models in Verilog for the different flavors of IOs.
.Build verification plan and verify the design including both behavioral models and transistor level implementation.
.Experience in System Verilog assertions(SVA), Power aware verification and formal verification is necessary.
.Debug issues at IP level and SoC level.
.Prior experience in analog/mixed signal simulations is preferred.
.Solid understanding of VLSI circuits and Spice simulator experience along with commercial characterization tool experience is expected.
.Understand the I/O circuit architecture and write stimulus for Timing/Power characterization.
.Need to be familiar with various Liberty models including NLDM, CCS, LVF.
.Work with internal customers to understand the requirements and support the SoC team on behavioral models and timing models throughout the design cycle.
.Exposure to RTL to GDSII flow is required. Understanding of STA and exposure to the flow is necessary.
.Interaction with tool vendors to drive the flow improvements and methodologies to address the requirements from latest technologies
.Solid understanding of VLSI circuits and Spice simulator experience along with commercial characterization tool experience is expected.
.Drive and build automation with any of the scripting languages like Python/Perl/TCL to improve the productivity and quality.
.Responsible for developing new methodologies and flows to support complex designs, driving the design verification reviews, automation and drive productivity & quality.
需求人數
1~1人
學歷要求
大學(學院)以上
科系要求
資訊工程相關、電機電子工程相關、其他工程相關
上班時段
日班
休假制度
依公司規定
職務類別
Analog IC Design Engineer
Semiconductor Engineer
11 ~ 30 應徵者