1. Responsible for the digital back-end physical implementation from netlist to GDS, completing the chip sign-off process. 2. Complete the full-chip floorplanning, including chip partitioning, power and ground network, placement of critical modules, utilization optimization, pin assignment. 3. Complete the overall digital back-end design of the chip, including placement, clock tree implementation, timing closure, power calculation, IR drop analysis, SI closure, and physical verification. 4. Co-work with front-end design team for the logic, clock and timing optimization. 5. Co-work with package team for the substrate design and SIPI simulations.