此為2025研發替代役招募預先公告，正式開放申請時間，請以NVIDIA Career Website官方公告為主:

https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite?q=RDSS&locationHierarchy1=2fcb99c455831013ea52ed162d4932c0

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

With the continuous improvement of chip technology, design scale and performance/power ratio, the physical design of digital chips is facing outstanding challenges in high frequency, low power consumption and multiple applications. High efficiency, high quality of the implementation of the construction chip is the guarantee of the company's competitiveness. As an ASIC-PD engineer at NVIDIA, you'll be responsible for the stage from RTL frozen to tape out, include synthesis, formal verification, constraints definition, timing closure/sign off, study on the timing impact of process and related methodology work. You will face the biggest challenge based on the most advanced process on building chips in the world.

What you'll be doing:

• Chip integration and netlist generation

• Synthesis

• RTL/netlist quality check

• Formal Verification

• Constraints creation and validation, timing budget.

• Work with ASIC team to analyze/resolve special timing issues.

• Cross-Team collaboration to implement chip partitioning and floorplan

• Work in conjunction with PR engineers to achieve timing closure for both partition and full chip level

• Achieve special mode timing closure, such as io, test, clock, async etc.

• Function eco creation

• Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout)

• Flow automation development for above areas

• Methodology in any of above areas.

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What we need to see:

• MS in EE or Microelectronics is preferred

• Project experience in IC design implementation

• Courses taken in circuit design, digital design

• Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is helpful

• Proficient user of Python or TCL is helpful

• Proficient in English reading and writing