Job Title: NPU Modeling Engineer Job Description: Overview: We are seeking an experienced NPU Architect to join our team. As an NPU Architect, you will play a crucial role in designing and implementing the hardware model for our Neural Processing Unit. Your expertise will be instrumental in ensuring efficient and accurate execution of neural network workloads on our NPU. Responsibilities: 1. NPU Architecture Design: • Collaborate with cross-functional teams to define the architecture and specifications for the NPU. • Design the NPU's core components, including the PE array, memory hierarchy, and control logic. • Optimize for performance, power efficiency, and scalability. 2. Bit-True Hardware Model Implementation: • Develop a bit-true hardware model of the NPU in C language. • Ensure that the model accurately represents the NPU's behavior, including arithmetic operations, memory access, and control flow. • Validate the model against reference neural network workloads. 3. Cycle-Accurate Modeling: • Create a cycle-accurate model of the NPU to simulate its behavior at the clock cycle level. • Account for pipeline stages, data dependencies, and timing constraints. • Use tools like Verilog, system-Verilog, or specialized simulation environments to achieve cycle-accurate modeling. 4. Performance Analysis and Optimization: • Profile the NPU model to identify bottlenecks and areas for improvement. • Propose and implement optimizations to enhance performance and reduce latency. • Collaborate with software teams to fine-tune the NPU's behavior. 5. Verification and Validation: • Create testbenches and test vectors to validate both the bit-true and cycle-accurate models. • Conduct functional and performance testing to ensure correctness and compliance with specifications. • Debug and resolve any discrepancies between the models and the actual NPU. 6. Documentation and Communication: • Document the NPU architecture, design decisions, and implementation details. • Present findings, progress, and challenges to stakeholders and management. • Collaborate with software engineers, firmware developers, and system architects. Qualifications: • Master's or Ph.D. degree in Electrical Engineering, Computer Science, or a related field. • Minimum of 3 years of experience in NPU architecture design and implementation. • Proficiency in C/C++/Verilog/System-Verilog programming for hardware modeling. • Familiarity with systolic arrays, matrix multiplication, and neural network accelerators. • Knowledge of bit-true modeling, fixed-point arithmetic, and floating-point arithmetic. • Experience with verification tools and simulation environments. • Strong analytical and problem-solving skills. • Excellent communication and teamwork abilities. • Attention to detail and commitment to quality. If you are passionate about NPU architecture, hardware modeling, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI!

Job Title: AI Compiler Engineer Job Description: Overview: We are seeking a skilled and motivated AI Compiler Engineer to lead the development of our AI compiler for the Neural Processing Unit (NPU). As part of our team, you will play a critical role in transforming high-level neural network workloads (such as CNNs and transformer models) into efficient machine code that maximizes inference performance, minimizes power consumption, and optimizes memory usage. Responsibilities: 1. Compiler Development: • Design and develop an AI compiler that translates high-level neural network descriptions (in frameworks like TensorFlow, PyTorch, or ONNX) into optimized machine code for the NPU. • Implement parsing algorithms to analyze neural network graphs and extract relevant information for compilation. 2. Optimization Strategies: • Optimize the computational graph by applying techniques such as operator fusion, kernel selection, and memory layout transformations. • Minimize inference time, reduce power consumption, and optimize memory footprint through intelligent code generation. 3. Performance Profiling and Analysis: • Profile compiled code to identify bottlenecks and areas for improvement. • Collaborate with hardware architects to understand NPU microarchitecture and tailor optimizations accordingly. 4. Code Generation and Lowering: • Generate efficient machine code from the intermediate representation of neural network operations. • Ensure compatibility with the NPU's instruction set architecture. 5. Integration and Testing: • Integrate the AI compiler into the overall software stack, including runtime libraries and drivers. • Develop test suites to validate correctness, performance, and compatibility across various neural network models. 6. Documentation and Communication: • Document design decisions, algorithms, and implementation details. • Collaborate with cross-functional teams, including hardware engineers, software developers, and researchers. Qualifications: • Master's or Ph.D. in Computer Science, Electrical Engineering, or a related field. • Minimum of 3 years of experience in compiler development, preferably with exposure to AI or machine learning. • Proficiency in C/C++/Python programming and familiarity with compiler construction. • Knowledge of neural network frameworks (TensorFlow, PyTorch, etc.) and their intermediate representations. • Experience with performance profiling tools and optimization techniques. • Understanding of machine learning concepts and hardware architectures. • Familiarity with data structures, optimization algorithms, and DevOps tools (such as Git, CI/CD pipelines). • Strong problem-solving abilities and attention to detail. • Excellent communication skills for collaborating with cross-functional teams. Preferred Skills: • Familiarity with deep learning frameworks and libraries. • Knowledge of hardware acceleration technologies and frameworks. • Experience of tensor computation and optimization. • Previous work in compiler for CPU, GPU, DSP, NPU is a plus. If you are passionate about compiler engineering, AI optimization, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI acceleration.

讓我們跨越國界，千里來相逢，用AI展翅翱翔，來尋找千載難逢的機會 (Tranxform.com 千逢科技) Hardware design verification : • Develop verification environment. • Co-work with hardware designers to verify designs with system verilog and system verilog assertion. • Building, maintaining testbenches and their components using UVM-based methods. • Functional coverage and code coverage. • Generating the random testcases for NPU design,and providing debug reports. • Develop the auto-verifying environment using scripting languages like Perl and Python. Programming Languages: Strong programming skills in languages like System Verilog, Verilog and possibly high-level languages like C/C++. Experience in AI/ML: In-depth knowledge of artificial intelligence and machine learning algorithms. NPU Architecture: Proficiency in designing Neural Processing Unit architectures. Parallel Processing: Understanding of parallel processing and optimization techniques for neural networks. Team Collaboration: Effective communication and collaboration skills within a multidisciplinary team. Problem-solving: Strong analytical and problem-solving skills to address complex design challenges. Knowledge of Industry Trends: Awareness of the latest trends and advancements in NPU technology and AI hardware. Results-Driven: A proactive and results-driven mindset, aiming for high-quality outcomes. Ownership Mentality: Willingness to take ownership and responsibility for the design process. Adaptability: Ability to adapt to evolving technologies and project requirements. Advanced Degree: Typically, a relevant advanced degree (Master's or Ph.D.) in Electrical Engineering, Computer Science, or a related field.

Job Title: Generative AI Models Optimization Engineer - NPU Hardware Job Description: Overview: We are seeking a skilled and innovative Generative AI Models Optimization Engineer to join our dynamic team. In this role, you will be responsible for developing and optimizing generative AI models specifically tailored for Neural Processing Unit (NPU) hardware. As a key member of our AI research and development team, you will play a crucial role in advancing the efficiency and performance of our cutting-edge AI applications. Responsibilities: Generative AI Model Development: Design, implement, and optimize generative AI models for deployment on NPU hardware. Collaborate with cross-functional teams to understand application requirements and tailor models for specific use cases. NPU Hardware Optimization: Analyze and profile NPU hardware architecture to identify optimization opportunities. Implement and fine-tune algorithms to maximize performance and minimize resource utilization on NPUs. Performance Evaluation: Conduct rigorous testing and performance evaluations to ensure generative AI models meet quality standards and deliver optimal results on NPU hardware. Collaborate with QA teams to establish benchmarking criteria and validate model performance across various scenarios. Algorithmic Efficiency: Work on enhancing algorithmic efficiency to ensure that generative AI models are capable of real-time generation while maintaining high-quality outputs. Implement and experiment with state-of-the-art techniques for model compression and quantization. Collaboration: Collaborate with hardware engineers, software developers, and researchers to integrate optimized models into end-to-end AI systems. Provide technical expertise and guidance to cross-functional teams. Documentation: Document optimization methodologies, best practices, and performance results. Create clear and comprehensive documentation for both technical and non-technical stakeholders. Qualifications: Master's or Ph.D. in Computer Science, Electrical Engineering, or a related field. Proven experience in developing and optimizing generative AI models. Solid understanding of Neural Processing Unit (NPU) architecture and hardware constraints. Proficiency in programming languages such as Python, TensorFlow, PyTorch, or C++. Experience with model compression, quantization, and other optimization techniques. Strong problem-solving skills and the ability to work in a collaborative team environment. Preferred Skills: Familiarity with deep learning frameworks and libraries. Knowledge of hardware acceleration technologies and frameworks. Experience with parallel computing and distributed systems. Previous work on AI applications in computer vision, natural language processing, or speech recognition is a plus. If you are passionate about pushing the boundaries of AI optimization on NPU hardware and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of generative AI applications.

讓我們跨越國界，千里來相逢，用AI展翅翱翔，來尋找千載難逢的機會 (Tranxform.com 千逢科技) Hardware Design • Generative AI NPU design and hardware architecture • Memory system design (cache controller, DRAM controller) • Interconnect/Fabric design • Low power technology expertise • High-speed interface design (HW/SW collaboration) • High-performance virtualization designs Programming Languages: Strong programming skills in languages like Verilog and possibly high-level languages like C/C++. Experience in AI/ML: In-depth knowledge of artificial intelligence and machine learning algorithms. NPU Architecture: Proficiency in designing Neural Processing Unit architectures. Parallel Processing: Understanding of parallel processing and optimization techniques for neural networks. Team Collaboration: Effective communication and collaboration skills within a multidisciplinary team. Problem-solving: Strong analytical and problem-solving skills to address complex design challenges. Knowledge of Industry Trends: Awareness of the latest trends and advancements in NPU technology and AI hardware. Results-Driven: A proactive and results-driven mindset, aiming for high-quality outcomes. Ownership Mentality: Willingness to take ownership and responsibility for the design process. Adaptability: Ability to adapt to evolving technologies and project requirements. Advanced Degree: Typically, a relevant advanced degree (Master's or Ph.D.) in Electrical Engineering, Computer Science, or a related field.

1. 具自動化視覺檢測設備開發經驗 2. 基本光學(相機、鏡頭、光源、模組)設計與規劃 3. 具Halcon 程式設計能力 4. 熟C#物件化程式架構 5. 二年以上工作經驗

Job Title: Firmware Engineer - NPU Driver Development Job Description: Overview: We are seeking a talented and experienced Firmware Engineer to join our team. In this role, you will be responsible for developing and optimizing firmware for our cutting-edge Neural Processing Units (NPU). You will work closely with both software and hardware engineers to ensure seamless integration and high performance of our NPU solutions. If you are passionate about embedded systems and have a strong background in firmware development, we would love to hear from you. Responsibilities: - Design, develop, and optimize firmware for Neural Processing Units (NPU). - Implement and maintain low-level drivers for NPU hardware. - Collaborate with hardware engineers to ensure seamless integration of firmware with hardware components. - Conduct performance analysis and optimization of NPU firmware. - Debug and resolve firmware issues, ensuring high reliability and performance. - Develop and execute test plans to validate firmware functionality. - Document firmware design and development processes. - Perform FPGA verification to validate NPU firmware and hardware integration. - Develop and maintain FPGA test benches and simulation models. Qualifications: - Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a related field. - 3+ years of experience in firmware development, particularly in embedded systems. - Proficiency in C/C++ programming languages. - Experience with embedded CPUs and development tools for runtime driver development. - Knowledge of NPU or GPU architecture and programming. - Familiarity with debugging tools such as JTAG, Logic Analyzers, and Oscilloscopes. - Strong problem-solving skills and attention to detail. - Excellent communication and teamwork abilities. - Experience with FPGA verification and validation processes. - Knowledge of FPGA design tools and simulation tools. Preferred Skills: - Experience with AI accelerator projects. - Knowledge of machine learning frameworks and libraries. - Familiarity with real-time operating systems (RTOS) and embedded Linux. If you are passionate about firmware development, AI optimization, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI acceleration

1. SoC/ASIC/Testchip & package architecture designs for high speed Analog/Serdes, D2D, and HBM2/3/4 integrations (Server, Networking, Wireless, AI, AR). 2. Execute SI/PI/EMC design-optimization for chip/package/system integration and electrical performance optimization, e.g., eye diagram, jitter, IR/EM, system-PI, cross-talk, and SSN/SSO. 3. Develop system integration design guidelines with SI/PI total solution for advanced packaging technologies (InFO/CoWoS/3D-IC). 4. Working as R&D with customers on technology competitive analyses, and develop chip/package/system technology road map for future productivity.

1. SoC/ASIC/Testchip & package architecture designs for high speed Analog/Serdes, D2D, and HBM2/3/4 integrations (Server, Networking, Wireless, AI, AR). 2. Execute SI/PI/EMC design-optimization for chip/package/system integration and electrical performance optimization, e.g., eye diagram, jitter, IR/EM, system-PI, cross-talk, and SSN/SSO. 3. Develop system integration design guidelines with SI/PI total solution for advanced packaging technologies (InFO/CoWoS/3D-IC). 4. Working as R&D with customers on technology competitive analyses, and develop chip/package/system technology road map for future productivity.

Trouble shooting/ Data searching

• Participate in sub-blocks and module-blocks floor planning and routing from scratch. • Perform layout blocks verification with sign-off in area (such as DRC, LVS, ANT, ERC & PERC) and troubleshooting the results. • Good hands-on experience in analog layout device matching techniques, high speed shielding and validation, as well to have acquired broader knowledge in handling high voltage devices. • Co-work with architect, design lead, designers, layout lead and layout engineers to achieve modules/full chip integration, place and route, chip level verification and tape-out. • Responsible for layout optimization, post layout extraction and parasitic analysis by ensuring analog and mixed signals circuits meet chip level tape-out, sign-off at desired area, performance, and power. • Specific technical expertise is desired in a broad range of process technologies from Bipolar, CMOS, DMOS (BCD) to FinFET advance node in complex, high-performance analog and mixed signals circuits layout. • Proactively look for continuous improvement opportunities in the complete layout flow methodologies (flow, layout, and design) as well as develop accurate IC layout design schedules and resource estimates.

1.Design and develop wireless comunication embedded SoC firmware and participate in system development phases. 2.Develop engineering level documentation and resource requirements. 3.Customer engagement and product design-in support 4.Will involve in working with customer's developing team, AE/FAE team

1.負責總務管理，包括團膳、廠區安全保全、廠區環境維護、清潔人員管理、廢棄物處理、公務車等業務。 2.空間管理，包括空間規劃和辦公區管理。 3.制定行政總務管理規章和機制，確保辦公室運作順暢。 4.督導並落實廠區服務之日常管理。 5.承接主管交辦專案和行政相關工作。

1. 差勤管理 2.招募聯繫 3.行政文書處理 4.文件管理 5.會計帳務處理 6.配合會計師各項帳務作業 7.會計師往來聯繫窗口 8.請購、採購作業 9.辦公室庶務 10.鼎新ERP操作 11.其他主管交辦事項

1.協助IC功能測試和驗證。 2.實驗室設備管理和維護。 3. 整理測試數據(Excel, Power Point)，並撰寫測試報告供內部團隊或客戶參考，需具有英文能力及工程背景。

1. 協助處理客戶訂單事宜，包括備貨、理貨、出貨。 2. 鼎新workflow ERP 表單資料登打(業務.生管.財務) 3. 倉儲管理助理及協助處理進出口文件資料。 4. 支援其他部門業務（如：採購、業務、財務）。 5. 主管交辦事項處理。

【工作內容】 1. 負責海外電子商務平台與企業官網的日常營運 2. 活動內容發想及文案撰寫 3. 分析及編製營運資料及報表 4. 市場調查，趨勢研究，競爭分析 5. 定期追蹤網站數據與分析檢討活動成效，配合達成業績目標 6. 其他主管交辦專案事項 【我們期待】 <能力需求> 能適應快節奏環境工作。 英文(TOEIC 750+)，英文concall。 <加分條件> 具海外電商(美、歐、日、澳)營運經驗，熟習各市場當地電商營運操作。 操作過Amazon、Ebay、樂天、Shopify等國際電商平台。 具數位行銷、內容行銷、網紅行銷等操作經驗。 待過品牌端，具美、歐、日電商零售品牌營運經驗。

1. WLAN MAC 軟/韌體開發與架構設計 2. 軟硬體 MAC 協同開發設計 3. WLAN USB/SDIO driver 之開發 4. 有QoS / Data Flow Control 設計經驗者尤佳

1. 負責指定 driver 之 FPGA 及 chip 端驗證 2. 協助硬體部門做測試,驗證 3. 協同硬體部門,參與 driver spec 之訂定 4. 負責指定 driver 之 porting 5. 協助 FAE 部門,完成客戶端要求之新功能

1. 負責指定 driver 之 FPGA 及 chip 端驗證 2. 協助硬體部門做測試,驗證 3. 協同硬體部門,參與 driver spec 之訂定 4. 負責指定 driver 之 porting 5. 協助 FAE 部門,完成客戶端要求之新功能