Salary & Location
Salary negotiable
(Regular monthly salary of NT$40,000 or above)
新竹市
Required
Work Experience
不拘
Job Description
[job description]
Wolley is seeking candidates for a digital design engineer position. You will join an experienced team designing next-generation memory, storage controllers, and high-speed interface standard.
You will also contribute to design concept discussion, architecture definition, as well as design implementation.
‧ Architecture design and RTL implementation
‧ System bus and related peripheral designs
‧ SoC and emulation platform design
‧ SoC system performance analysis
[Requirement]
1. Bachelor's or Master's degree in Electrical Engineering or related fields
2. Familiar with RTL design, SystemVerilog, front-end design flow
3. The following working knowledge is desired:
* Python programming
* TCL scripting
* Universal Verification Methodology (UVM)
* Low power design and analysis
Educational Requirements
大學(學院)以上
Field of Study Requirements
電機電子工程相關、其他工程相關
Work Schedule
日班
Leave Policy
週休二日
Job Skills
Hardware Language Programming
Digital Chip Product Development
Digital Circuit Analysis & Design
Digital Circuit Verification
撰寫硬體語言程式 數位晶片產品開發 數位電路分析設計 數位電路驗證
Job Category
Electronics Engineers
Digital IC Design Engineer
Telecommunications/Communication System Engineer
新竹市
IC設計相關業
瓦雷科技成立於2016年，由多位資深IC設計與記憶體/存儲領域專家在舊金山及新竹共同創立，2021年底完成B輪募資。目前董事會包含：創辦人項春申博士、創意電子前總經理賴俊豪先生、Marvell創辦人Dr. Sehat Sutardja、旺宏電子微電子及記憶體事業群副總經理倪福隆先生等四位成員。(https://www.wolleytech.com/index.php/menu-about-us/menu-board-of-director)
瓦雷科技多年來深耕記憶體領域，專注於擴展客戶所需之軟硬體設計，協助全球客戶實現各項加值需求。以無需查表SCM控制器及PCIe/CXL IP技術為基礎，瓦雷科技提出CXL Native Memory、 NVMe-over-CXL 與 CXL Persistent Memory等產品概念，在減少晶片尺寸、降低功耗、提升效能等方面具有顯著優勢，尤其適用於解決 AI PC 或者資料中心在執行大型語言模型等各式應用所遭遇的記憶體/存儲運算瓶頸。
CXL為全球發展重點。瓦雷科技之CXL成果獲聯盟官方與Xilinx認可列於供應商名單，與客戶合作之PCIe/CXL FPGA驗證平台也於2023年2月通過PCI-SIG compliance認證；有助於推升台灣廠商對於CXL技術之掌握及加速產品開發，共享市場商機，前景值得期待。
