新加坡商優思特股份有限公司台灣分公司
SI Validation Engineer
11/12 更新
全職
初階
英文 條件要求
6 ~ 10 應徵者

職務概況

待遇面議
(經常性薪資達 4 萬元或以上)
台北市南港區

條件要求

語文條件
英文
聽/中等、說/中等、讀/中等、寫/中等
工作經歷
不拘

職務描述

This SI Validation Engineer will conduct simulation service for Data center customer for their board design check. The work is including Channel Check Tool and OOG design review. Will be responsible for simulation post data process, report wrap up for customers, Workstation maintenance, Software upgrade, scripting development and work with 3rd party vendor for SI tool enhancement. Needs to possess the following skill to carry out the project tasks:
1. Familiar with Cadence Power SI, Sigrity, Speed 2000, Power DC simulation software and tool manipulation.
2. Familiar with Python Language and experienced in programing c.
3. Good reading and writing in English.
4. Need to manipulate tools to conduct simulations including CCT for customer’s board design.
5. 3rd party tool maintenance - Cadence Power SI, Speed 2000, and workstation maintenance.
6. Software script development for Report Post analysis.
The candidate is adept in:
a) Signal Integrity
b) CCT (Speed2K)
c) FD-CCT (PowerSI, SystemSI, FastCCT)
d) Result post process (Python)
需求人數
1~1人
學歷要求
專科以上
上班時段
日班
休假制度
週休二日
職務類別
Electronics Engineers
Telecommunications/Communication System Engineer
6 ~ 10 應徵者