立宥成科技有限公司
Digital ASIC engineer
10/7 更新
Array
全職
經理/總監
0 ~ 5 應徵者

職務概況

待遇面議
(經常性薪資達 4 萬元或以上)
新北市新店區

條件要求

工作經歷
5年以上

職務描述

1. What you‘ll be doing
* You‘ll be responsible for transferring Matlab model into RTL design and silicon bring up at IP or full-chip level for all sensor products
* Sometimes you have to do system integration and performance trade-offs
* Sometimes you‘ll have to do FPGA design for verification
2. What we need to see
* Solid background on Verilog and ASIC design, including RTL coding, simulation, verification, debugging, synthesis, DFT, LEC, STA.
* Familiar with Mathwork Matlab is a must
* Familiar with perl script is a plus
* ARM M0 series(AHB/APB) integration experience is a plus
* System Verilog is a plus
* Exposure of UVM methodology is a plus
* Excellent communication skills. Good team work spirit, easy to cooperate with team members
歡迎所有求職者
需求人數
1~1人
學歷要求
大學(學院)以上
上班時段
0900~1800
休假制度
週休二日

工作技能

Digital Chip Product Development
數位晶片產品開發
職務類別
Digital IC Design Engineer
Analog IC Design Engineer
0 ~ 5 應徵者