1. What you‘ll be doing * You‘ll be responsible for transferring Matlab model into RTL design and silicon bring up at IP or full-chip level for all sensor products * Sometimes you have to do system integration and performance trade-offs * Sometimes you‘ll have to do FPGA design for verification 2. What we need to see * Solid background on Verilog and ASIC design, including RTL coding, simulation, verification, debugging, synthesis, DFT, LEC, STA. * Familiar with Mathwork Matlab is a must * Familiar with perl script is a plus * ARM M0 series(AHB/APB) integration experience is a plus * System Verilog is a plus * Exposure of UVM methodology is a plus * Excellent communication skills. Good team work spirit, easy to cooperate with team members 歡迎所有求職者

1.系統層級的設計及驗證 2.有 verilog RTL code design 5 年以上經驗 3. 配合度良好者 歡迎所有求職者